1. Field of the Invention
The present invention is generally directed to a scan path circuit utilized for inspecting an interior of an integrated circuit, and more particularly, to an improvement for expanding an applicable range thereof.
2. Description of the Related Art
In recent years, the technology in the sector of semiconductors has remarkably been developed, wherein an integrating factor of LSIs becomes increasingly large, and circuit elements loaded on the single LSI also increase in number. For this reason, the circuit manufactured on the LSI has a larger scale and more complicated functions than ever before.
When testing such an LSI, direct observation into and control over the LSI interior are difficult, and hence it is a common practice that these operations are effected by inputting input data (test data) and observing output data thereof. Namely, presumption about presence or non-presence of faults is given by checking whether the output data relative to the predetermined test data are normal or not. Where the circuit is large in scale and complicated, however, there arise problems in which an amount of test data required for such testing extremely increases, and the time needed for creating the test data is also increased. The amount of test data is large, and the time taken for testing elongates correspondingly.
To obviate such problems and facilitate the testing on the LSI, a testing circuit unnecessary for a normal operation is added, or the circuit is modified for the testing.
On the other hand, the users become capable of designing the LSIs because of a wide spread of a computer aided design (CAD), such attempts are now made in many ways. In this case, the addition or modification of the circuit for facilitating the testing has to be effected on the part of users. However, the design taking the testing into consideration is quite difficult and requires a work of time. Under such circumstances, it is not easy for the users to provide the designs associated with the testing, which is in turn a drawback to the development of LSIs.
Hence, if there is provided a testing system capable of facilitating the testing and automatically performing the design, efficiencies in design modification, in creation of input data and in testing can be improved, which will increase the merits of utilization thereof.
A first reason why the testing on the LSI is difficult lies in the fact that values of flip-flops incorporated into the circuit are difficult to be directly observed or controlled from outside.
For the purpose of eliminating the foregoing problems, a scan design has heretofore been adopted. An arrangement of the scan design is that the flip-flops as a storage circuit in the integrated circuit are so connected that they are usable as a shift register, and a testing route is specially provided. Based on this scan design, since the flip-flops are employed as the shift register, desired values can be set in the flip-flops, and the values of the flip-flops can be outputted to the outside. Besides, the scan design exhibits an effect in which the circuit design for testablity can automatically be provided.
The description will now deal with a prior art scan path circuit in conjunction with FIG. 13. Referring to FIG. 13, flip-flops 10 and 12 are incorporated into a logic circuit 100. The flip-flops 10 and 12 in the logic circuit 100 are connected in series through switches 14 and 16.
The flip-flops are separated from the logic circuit by changing over the switches 14 and 16, whereby the flip-flops are allowed to function as a shift register.
More specifically, when turning on the switches 14 and 16 in response to mode control signals during the testing, the flip-flops 10 and 12 are connected in series, thus acting as the shift register. Therefore, outputs of the shift register (flip-flops 10 and 12) can be outputted to the outside (scan out) while carrying out a shifting operation in accordance with scan inputs. As a result of this, the values of the flip-flops 10 and 12 can be checked. In addition, the values of the flip-flops incorporated into the circuit can be set to predetermined values by inputting the predetermined values to the shift register (flip-flops 10 and 12) (scan-in) while performing the shifting operation. In this case, the operations of the flip-flops are controlled on the basis of external clock signals in order that the flip-flops 10 and 12 are made to exhibit a function of the shift register.
As above-mentioned, the scan design facilitates the circuit testing in the LSI by observing and controlling the values of the flip-flops as storage elements.
There are, however, caused the following problems inherent in the prior art scan design.
(a) According to the scan design, the flip-flops in the circuit serve as not only an ordinary storage circuit but also a scanning shift register during the testing. For this reason, the flip-flops to which this scan design is applied have to be designed to operate in synchronism with the external clock.
Hence, the scan design can not be applied to a circuit including the flip-flops asynchronous with the signals from the external clock.
(b) The scan design can not be applied to a combinational circuit and to a circuit including a loop circuit which is not in the form of flip-flop, e.g. a loop circuit designed to form a signal line loop by feeding back a part of the signal line.
The circuit including the flip-flops asynchronous with the external clock signals or the circuit including the loop circuit which does not take the form of flip-flop are not peculiar, or rather often employed in the ordinary circuit design. In such circuits, a circuit design for testablity is also required.
A circuit modification has heretofore been effected manually so that the scan design can also be applied to those circuits. The operations of modifying those circuits are performed not by automatic conversion but by hands. Therefore, where the scan design is applied to those circuits, the merits are very small.
Furthermore, the circuits to which the scan design is allowed to be applied are attended with the following problems.
That is, the ordinary flip-flops can be converted into flip-flops dedicated to scanning and having a shift function by use of an automatic conversion system. However, a scanning flip-flop circuit having the shift function and a storage function as well is typically quite complicated in structure. Therefore, an additional problem is that a normal operation is delayed as compared with the flip-flops invested with no scan function.